This invention relates to thin film transistors (hereinafter termed TFTs), particularly to top-gate self-aligned TFTs. Such transistors may be used, for example, in active-matrix liquid-crystal displays, or other large-area electronic devices. The invention relates principally to methods of manufacturing such transistors.
There is much interest in developing thin-film circuits including TFTs on insulating substrates for large-area electronics applications. For example, TFTs fabricated with portions of an amorphous or polycrystalline semiconductor film may form the switching elements in a matrix of liquid crystal display pixels or in a large-area image sensor array.
The present invention is directed to top-gate thin film transistor structures. Compared to a bottom-gate TFT, an important advantage of a top-gate TFT is the ease with which a low resistance gate line can be made with a highly conductive top-gate metal such as aluminium. The gate line resistivity is of particular importance when considering the performance of amorphous silicon TFTs in order to make them suitable for active-matrix addressing of large, high resolution displays. Also of importance is the ability to form a self-aligned TFT structure. Such a structure reduces the parasitic source-drain capacitance and improves the large area uniformity of the residual capacitance.
A known technique for forming a self-aligned top-gate TFT structure involves the use of so-called xe2x80x9cback exposurexe2x80x9d through the substrate of a negative resist layer, the resist pattern then being used as a mask during subsequent etching to form the gate electrode pattern. JP-A-63-47981 discloses a top-gate thin film transistor manufactured using this method. The lower source and drain electrode pattern must be formed from an opaque material so that the exposure of the negative resist through the substrate is aligned with the spacing between the source and drain electrodes. This gives rise to a self-aligned TFT structure. However, the TFT structure, including the gate electrodes, must be transparent to enable exposure through those layers of the negative resist. It is therefore not possible to use this back exposure technique in conjunction with low resistance metal gate lines, such as aluminium gate lines, which are opaque. JP-A-63-47981 discloses the use of a transparent indium tin oxide (ITO) gate electrode pattern through which exposure of the negative resist can take place.
The transparent ITO gate requires a separate deposition step in a separate system to that used for the TFT stack. For example, the TFT stack may be formed using a PECVD system, whereas the ITO layer will be sputtered.
According to the present invention, there is provided a method of manufacturing a thin film transistor comprising;
forming a substantially opaque source and drain electrode pattern on a substrate;
depositing a substantially transparent silicon film on the source and drain electrode pattern to provide a transistor body comprising a channel area of the transistor;
depositing a substantially transparent gate insulator layer and a substantially transparent amorphous silicon gate electrode layer over the channel area;
depositing a layer of negative resist over the gate electrode layer;
exposing the layer of negative resist using back exposure through the substrate, thereby defining an exposed region substantially aligned with the spacing between the source and drain electrodes;
removing the unexposed resist layer and the gate electrode layer beneath the unexposed resist layer;
removing the exposed resist layer; and
processing the remaining amorphous silicon gate electrode layer to lower its resistance.
The invention enables the use of an amorphous silicon layer to form the gate electrode layer. In the case of an amorphous silicon TFT, this layer can be deposited as part of the TFT in a single run of a PECVD deposition system without breaking the vacuum. The deposition and processing of amorphous silicon layers is already required in the manufacture of the TFT, so that no additional equipment is required and there is almost no change in throughput. The step of processing the amorphous silicon gate electrode layer to lower its resistance enables the gate to function correctly.
A problem with the use of a transparent gate electrode layer in a top-gate TFT is that the transparency gives rise to a high sensitivity of the transistor to light exposure. This may be a particular problem for the use of the TFTs as the switching devices for an array of liquid crystal display pixels or as the switching devices in a large-area image sensor device. However, a transparent gate electrode layer is required to enable back exposure of the negative resist. Preferably, therefore, the processing additionally increases the attenuation of electromagnetic radiation by the gate electrode layer. This enables the amorphous silicon gate electrode layer to be converted into a more opaque layer which acts as a partial light shield for the channel area of the TFT.
For this purpose, the processing step may comprise: depositing a chromium layer over the transistor; reacting the chromium layer to form chromium silicide with adjacent areas of the amorphous silicon gate electrode layer; and removing the unreacted chromium.
The chromium suicide layer reduces the gate contact resistance and also converts the amorphous silicon gate electrode layer into an opaque layer. The chromium silicide layer is self-aligned over the amorphous silicon gate electrode layer. Additional conducting layers may be provided to define upper row (or column) conductors, but these do not need to be aligned accurately with the TFT structure, since they are not performing a light shielding function for the TFTs.
The invention also provides a thin film transistor comprising: substantially opaque source and drain electrodes on a substrate; a silicon transistor body on the source and drain electrodes defining a channel area of the transistor; a gate insulator layer and a gate electrode layer over the channel area, wherein the gate electrode layer comprises a chromium silicide layer.